With the recent advance of higher processing speed, a microprocessor is provided with a primary memory device with a large capacity. To obtain the large capacity primary memory device, there has been proposed a memory device capable of accessing data at high speed at the sacrifice of random characteristics of data access, in order to solve a bottleneck with respect to low processing speed due to the low access speed of the external memory device.
An example of the memory device as described above has been proposed (not yet published) by the present inventor in Japanese Patent Application No. 3-255354, in which an address is acquired within a predetermined number of cycles of a basic clock supplied to the system and further data input and output starts a predetermined cycles after the cycle at which the address is acquired. In addition, Japanese Patent Application No. 4-638135 (not yet published) discloses a memory device provided with internal data registers, which operates as follows: a group of access data are stored in the internal registers temporarily for data access between the outside and the memory cells. The data to be stored in the registers are selected by scrambler circuits; that is, a scrambler control circuit controls the scrambler circuits so that access data can be stored cyclically in the respective registers at predetermined sequence for each cycle of a clock signal. Further, the data are inputted and outputted between the outside and the registers via an input/output buffer. In response to a head address indicative of data access start, a predetermined selection sequence of the scrambler circuits is determined.
The above-mentioned semiconductor memory device will be described in more detail with reference to FIG. 4. In FIG. 4, a column decoder 1 selects one of cell blocks CB1 to CB5 of a memory core 2. Each of the cell blocks CB1 to CB5 includes 4 columns CM1 to CM4. Data stored in the four columns CM1 to CM4 of one of the cell blocks CB1 to CB5 (selected by the column decoder 1) are outputted to data lines DLN simultaneously. The data on the data lines DLN are transferred to read/write data lines RWD via a data buffer 4. The read/write data lines RWD are connected to data registers 51 and 52 via scrambler circuits 61 and 62, respectively. A scrambler control circuit 7 controls the two scrambler circuits 61 and 62 so that the data on the read/write data line RWD can be selectively stored 2 bits by 2 bits in data areas R1, R2, R3 and R4 of the data registers 51 and 52, respectively. The data stored in the data registers 51 and 52 are selected by a data selection section 9 and then outputted through a data output buffer 8 as data output.
The operation of the memory device as shown in FIG. 4 will be described hereinbelow.
One block of the five cell blocks CB1 to CB5 of the memory cell 2 is selected by the column decoder 1. Data of the four columns CM1 to CM4 of the selected block are read simultaneously to the data lines DLN, and then transferred to the read/write data lines RWD via the data buffer 4. The four bit data are selectively stored 2 bits by 2 bits in the data areas R1, R2, R3 and R4 of the data registers 51 and 52, respectively via the scrambler circuits 61 and 62 controlled by the scrambler control circuit 7. For instance, the access sequence of the data areas R1, R2, R3 and R4 of the data registers 51 and 52 is as follows: R1, R2, R3 and R4. The data stored in the data areas R1, R2, R3 and R4 are selected by the data selector section 9, transferred to the data output buffer 8, and then outputted therefrom as the data output.
In the semiconductor memory device as described above, however, there exists a problem in that it is impossible to start data access beginning from any given bit of the columns CM1 to CM4, when data more than 4 bits (the number of data areas) are required to be outputted from the data areas R1, R2, R3 and R4 of the data registers 51 and 52. The reason is as follows: since the columns CM1 to CM 4 selected by the column decoder 1 are fixed, when 8-bit data are accessed, it is impossible to constitute 8-bit data by simply combining 2 sets of 4-bit data. In other words, it is impossible to obtain an 8-bit continuous access. For example, if the access sequence as "3"--"4"--"5"--"6"--"7"--"8"--"1"--"2" is required, the access sequence is inevitably determined as "3"--"4"--"1"--"2"--"5"--"6"--"7"--"8" or " 3"--"4"--"1"--"2"--"7"--"8"--"5"--"6". Although this problem can be solved by using more larger-scale registers or by scarificing the access speed, this method raises another problem in that the memory characteristics of the synchronous memory device are deteriorated.